The system mainly has 2 network ports, RGMII interface, running 100M, so the clock and signal are both 25M, but the FPGA internal clock is 125M.
During the RE test, it was found that the 3/5/7th harmonic of 125M exceeded the standard. . .
The clock amplitude of the network port has been changed. It can be a little smaller, but it is still too high. Adjusting the series resistance in the RGMII phy tx direction is invalid or worse.
Thank you
Hina 發表於 December 22, 2020
Hello, if there is a problem with EMC, first do not blindly rectify it, especially the clock frequency directly. The frequency used by the entire circuit does not exceed 200M, and the super positions are all between 350M-1G, so don't consider the clock frequency. I can’t say specifically. First of all, the circuit design is one aspect, and the other is the power supply (whether it is a switching power supply). It is best to say what product it is, so that you can better judge.
Buster 發表於 December 22, 2020
Is a 125MHz clock used in the circuit? Looking at this waveform at present, the power supply is unlikely.
Geena 發表於 December 22, 2020
At present, it is likely to be the odd harmonics of the 125MHZ clock, you can refer to it.
Jeanie 發表於 December 22, 2020
CR filter is added to the beginning of the clock line. The FPGA drive current is reduced. Absolutely.
