SN8P2501BPB

FEATURES

Memory configuration

ROM size: 1K * 16 bits.

RAM size: 48 * 8 bits.

4 levels stack buffer.

3 interrupt sources 

2 internal interrupts: T0, TC0

1 external interrupt: INT0

I/O pin configuration

Bi-directional: P0, P1, P2, P5.

Wakeup: P0, P1 level change

Pull-up resisters: P0, P1, P2, P5.

Input only: P1.1

Programmable open-drain: P1.0

External interrupt: P0.0 (PEDGE edge trigger)

3-Level LVD.

Reset system and power monitor.

Powerful instructions

Instruction’s length is one word.

Most of instructions are one cycle only.

All ROM area JMP/CALL instruction.

All ROM area lookup table function (MOVC).

Fcpu (Instruction cycle)

Fcpu = Fosc/1, Fosc/2, Fosc/4, Fosc/8, Fosc/16.

One 8-bit basic timer with RTC (0.5Sec). 

One 8-bit timer with external event counter, Buzzer and PWM. (TC0).

On chip watchdog timer and clock source is 

Internal low clock RC type (16KHz(3V), 32KHz(5V))

4 system clocks

External high clock: RC type up to 10 MHz

External high clock: Crystal type up to 16 MHz

Internal high clock: 16MHz RC type

Internal low clock: RC type 16KHz(3V), 32KHz(5V)

4 operating modes

Normal mode: Both high and low clock active

Slow mode: Low clock only. 

Sleep mode: Both high and low clock stop 

Green mode: Periodical wakeup by T0 timer

Package (Chip form support)

DIP 14 pin

SOP 14 pin

SSOP 16 pin

Features Selection Table

SYSTEM BLOCK DIAGRAM

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方向：

SONiX 8-Bit Micro-Controller