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ISO7220CDR

DGTL ISO 2500VRMS 2CH GP 8SOIC

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ISO7220CDR

DGTL ISO 2500VRMS 2CH GP 8SOIC

訂單滿$200即可獲贈限量版中式禮品一份.

訂單滿$200即可獲贈限量版中式禮品一份.

訂單金額超過1000 美元可減免30 美元運費.

超過5000 美元的訂單可免運費和交易費.

這些優惠適用於新客戶和現有客戶,有效期為2024年1月1日至2024年12月31日.

  • 製造商:

    TI

  • 規格書:

    ISO7220CDR datasheet

  • 包裝/箱:

    SOP-8

  • 產品分類:

    IC芯片

  • RoHS Status: RoHS 狀態 Lead free/RoHS Compliant

現在提交您的報價請求,我們期望在 5月 06, 2024內提供報價。現在就下訂單,我們期望在 5月 09, 2024內完成交易。時間是格林威治標準時間+8:00。

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ISO7220CDR 產品詳情

FEATURES

• 1, 25, and 150-Mbps Signaling Rate Options

– Low Channel-to-Channel Output Skew; 1 ns max

– Low Pulse-Width Distortion (PWD); 1 ns max

– Low Jitter Content; 1 ns Typ at 150 Mbps

• Typical 25-Year Life at Rated Voltage (see app. note SLLA197 and Figure 19) 

• 4000-Vpeak Isolation, 560 V peak VIORM

– UL 1577, IEC 60747-5-2 (VDE 0884, Rev 2), IEC 61010-1

– 50 kV/μs Typical Transient Immunity

• Operates with 3.3-V or 5-V Supplies

• 4 kV ESD Protection

• High Electromagnetic Immunity

• –40°C to 125°C Operating Range


APPLICATIONS

• Industrial Fieldbus

– Modbus

– Profibus™ – DeviceNet™ Data Buses

• Computer Peripheral Interface

• Servo Control Interface

• Data Acquisition


DESCRIPTION

The ISO7220 and ISO7221 are dual-channel digital isolators. To facilitate PCB layout, the channels are oriented in the same direction in the ISO7220 and in opposite directions in the ISO7221. These devices have a logic input and output buffer separated by TI’s silicon-dioxide (SiO2) isolation barrier, providing galvanic isolation of up to 4000 V. Used in conjunction with isolated power supplies, these devices block high voltage, isolate grounds, and prevent noise currents on a data bus or other circuits from entering the local ground and interfering with or damaging sensitive circuitry.

A binary input signal is conditioned, translated to a balanced signal, then differentiated by the capacitive isolation barrier. Across the isolation barrier, a differential comparator receives the logic transition information, then sets or resets a flip-flop and the output circuit accordingly. A periodic update pulse is sent across the barrier to ensure the proper dc level of the output. If this dc-refresh pulse is not received every 4 μs, the input is assumed to be unpowered or not being actively driven, and the failsafe circuit drives the output to a logic high state.

The small capacitance and resulting time constant provide very fast operation with signaling rates available from 0 Mbps (DC) to 150 Mbps.(1)The A- and C-option devices have TTL input thresholds and a noise filter at the input that prevents transient pulses from being passed to the output of the device. The M-option devices have CMOS Vcc/2 input thresholds and do not have the input noise-filter and the additional propagation delay.

These devices require two supply voltages of 3.3 V, 5 V, or any combination. All inputs are 5-V tolerant when supplied from a 3.3-V supply and all outputs are 4-mA CMOS.

These devices are characterized for operation over the ambient temperature range of –40°C to 125°C.

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